A conventional one-level arbiter decides a winner based on simple priority or a slot-based scheme. In a one-level arbiter, qualities such as priority, minimum or guaranteed latency, fairness and memory bandwidth efficiency result in a large and/or complicated design. A one-level arbiter does not allow intelligent decisions about what is best for the system as a whole for memory accesses.
It would be desirable to implement an arbiter for use with a memory (e.g., a double data rate (DDR) memory) using multi-level arbitration to make arbitration decisions to improve the performance of a memory subsystem.